Accepted PapersTotal of 114 papers were submitted to the workshop and the Program Committee selected 47 papers for the Proceedings. The acceptance ratio was 41%. The following 32 papers have been accepted for an oral presentation:
#21 Offline Phase Analysis and Optimization for Multi-Configuration Processors
#22 Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context
#26 A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design
#28 High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks
#30 Rapid Implementation and Optimisation of DSP Systems on SoPC Based Heterogeneous Platforms
#32 Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
#33 Configurable computing for high-security/high-performance ambient systems
#35 Reconfigurable Multiple Operation Array
#36 Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow
#41 Moving up to the modeling level for the transformation of data structures in embedded multimedia applications
#49 Observed power-efficiency trends of mobile communication devices
#50 Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques
#51 Hardware Cost Estimation for Application-Specific Processor Design
#53 Generating Stream Based Code from Plain C
#54 RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration
#57 Automatic FIR Filter Generation for FPGAs
#60 Ultra Fast Cycle-Accurate Compiled Simulation of Inorder Pipelined Architectures
#68 The ODYSSEY Framework for System-Level Synthesis of Object-Oriented Embedded Systems
#70 A Programming Model for An Embedded Media Processing Architecture
#73 A Radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
#74 CORDIC-Augmented Sandbridge Processor for Channel Equalization
#76 Data-driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
#84 Power Efficient Instruction Caches for Embedded Systems
#85 Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic
#86 Micro-Architecture Performance Estimation by Formula
#88 Fast Real-Time Job Selection with Resource Constraints under Earliest Deadline First
#101 Exploiting Intra-function Correlation with the Global History Stack
#105 Two-dimensional Fast Cosine Transform for Vector-STA Architectures.
#106 DVB-DSNG modem High-Level Synthesis in an optimized Latency Insensitive System context
#112 SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC
#114 Interprocedural Optimization for Dynamic Hardware Configurations
#119 A Scalable Embedded JPEG2000 Architecture
The following 15 papers have been accepted for a poster presentation:
#17 Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of Concept
#31 A Novel JAVA Processor for embedded Devices
#52 A Case for Visualization-integrated System-level Design Space Exploration
#55 FPL-3E: towards language support for reconfigurable packet processing
#61 Automatic ADL-based Assembler Generation for ASIP Programming Support
#63 First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption
#65 Tuning a Protocol Processor Architecture Towards DSP Operations
#69 DDM-CMP: Data Driven Multithreading on a Chip Multiprocessor
#82 Real-time Stereo Vision on a Reconfigurable System
#90 Formal Specification of a Protocol Processor
#92 Pattern Matching Acceleration for Network Intrusion Detection Systems
#96 Compressed Swapping for NAND Flash Memory Based Embedded Systems
#111 Application of Very Fast Simulated Reannealing (VFSR) to Power Optimization
#122 A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems
#125 Flex caches: What are they and why are they useful
The acceptance of the papers is conditional: at least one of the authors has
to register for the workshop. A 20 minute time slot is allocated for oral
presentations and a 5 minute time slot for poster presentations. All the
papers (accepted for oral or poster presentation) are in the same format, max. 10 pages, Springer
LNCS style. |
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